For any given level of general performance, a RISC chip will typically have far fewer transistors dedicated to the core logic which originally allowed designers to increase the size of the register set and increase internal parallelism.

Other features, which are typically found in RISC architectures are:

* Uniform instruction format, using a single word with the opcode in the same bit positions in every instruction, demanding less decoding.
* Identical general purpose registers, allowing any register to be used in any context, simplifying compiler design (although normally separate floating point registers)
* Simple addressing modes. Complex addressing performed via sequences of arithmetic and/or load-store operations
* Few data types in hardware, some CISCs have byte string instructions, or support complex numbers; this is so far unlikely to be found on a RISC.

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